[PDF.04ey] Design Space Exploration of Network-on-Chip at System level: A Genetic Algorithm Approach

Design Space Exploration of Network-on-Chip at System level: A Genetic Algorithm Approach

[PDF.ia46] Design Space Exploration of Network-on-Chip at System level: A Genetic Algorithm Approach

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 |  2012-01-11 | Original language:English | PDF # 1 |  8.66 x.37 x5.91l,.54 | File type: PDF | 160 pages

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||About the Author|Dr. Rabindra Kumar Jena is presently working as an Associate Professor (Information Technology) at Institute of Management Technology (IMT), Nagpur, India. He has degrees in M.Sc, M.Tech(CSE) and PhD from ABV-Indian Institute of Information Tec

About the Book: The goal of this text is to help students, researchers and academicians, who are working in the field of CAD for VLSI. Network-on-Chip(NoC) has been recently developed as an on-chip communication solution for System-on-Chip(SoC) design. This paradigm supports various communication resources at a time and overcomes the limitations of bus-based System. Design space exploration methodology at system level reduces the time-to-market pressure of the large an...

You can specify the type of files you want, for your gadget.Design Space Exploration of Network-on-Chip at System level: A Genetic Algorithm Approach   |  Rabindra Kumar Jena.Not only was the story interesting, engaging and relatable, it also teaches lessons.

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